This invention relates generally to integrated circuit design. More particularly, this invention relates to reducing power in dynamic circuits.
As more electronic circuits are included on a single die, the power dissipated by a single die continues to increase. In order to keep the temperature of a single IC (integrated circuit) at a reasonable temperature, many techniques have been used. For example, elaborate cooling fins have been attached to the substrate of ICs. Also, fans have been positioned near a group of IC""s to cool them. In some cases, liquids have been used to transfer the heat produced by ICs. These solutions can be costly and may require a great deal of space, where space is at a premium.
In addition, the cost to air condition rooms where many computers are stored can be costly. Another problem created by ICs consuming more and more power is that in some cases not enough power can be supplied to a computer system through a single-phase power source. In order to supply enough current for this type of computer system, more costly three-phase power is required. If the power used by ICs can be reduced while still achieving higher levels of integration, the cost and area of devices that use ICs may be reduced.
Dynamic logic is a common type of logic used when designing ICs. Typically, a node in a dynamic logic block is precharged to voltage close to the value of a supply, VDD, during the precharge phase of a clock. On the next phase, the evaluation phase, of the clock, a combination of logic (e.g. NAND, NOR, etc) in the dynamic logic block will either discharge the precharged node or leave the node charged. In this manner, a dynamic logic block performs logic functions.
When a node is not discharged during the evaluation phase of the clock, the node ideally would retain all its charge. However, the node leaks off charge. The charge lost on the node is replaced by charge through a FET (Field Effect Transistor), usually a PFET (P-type Field Effect Transistor), that is connected between a power supply VDD and the node. Even though this FET is xe2x80x9coffxe2x80x9d, subthreshhold leakage through the FET supplies charge to the node.
On an IC where many FETs are used to precharge dynamic logic blocks, subthreshhold leakage through these FETs can use a great deal of power. There is a need in the art to reduce the power consumed through subthreshold leakage in dynamic circuits.
One embodiment of this invention reduces the threshhold leakage in dynamic logic blocks by replacing individual smaller FETs used to precharge individual dynamic logic blocks with a larger single FET. The larger FET replaces only FETs that have the same signal controlling their gates. A detailed description of one embodiment of this invention is described later.
An embodiment of the invention provides a circuit and method for reducing power in dynamic circuits. A large single pre-charge FET is used to precharge the pre-charge nodes of all dynamic logic blocks contained in a plurality of dynamic logic blocks. The large single pre-charge FET replaces all smaller individual FETs that normally would be used. Because smaller FETs typically have more subthreshhold leakage than larger FETs, the overall subthreshhold leakage is reduced. The large pre-charge FET only replaces smaller pre-charge FETs that have the same pre-charge signal going to their gates.